The present invention relates to technology of a semiconductor device and particularly, to technology effective when applied to a semiconductor device having an SRAM (Static Random Access Memory).
In an electronic device desired to improve performance and increase speed, it is indispensable to mount a microcomputer and in the configuration of a microcomputer, packaging of a high-speed memory with a large capacity is desired. In particular, in order to realize higher-speed processing, it is demanded to increase the capacity of a cache memory. That is, a RAM used by a CPU (Central Processing Unit) of a computer when executing a control program etc. is desired to increase speed and capacity.
As such a RAM, a DRAM (Dynamic RAM) and an SRAM are used generally, however, at a part where high-speed processing is required, such as the above-described cache memory, an SRAM is used usually. As the structure of a memory cell of an SRAM, a high-resistance load type including four transistors and two high-resistance elements and a CMOS type including six transistors are known. In particular, the CMOS type SRAM has a very small leak current when holding data, and therefore, is highly reliable and the mainstream at present.
In general, in a memory cell, reduction in the area of element surface means not only downsizing of the memory cell array but also realization of high speed. Hence, various layouts of memory cell structure have been proposed in order to realize higher-speed operations of the SRAM. Particularly, in recent years, technology of a multiprocessor has been introduced as means for realizing high speed of a computer and it is demanded for a plurality of CPUs to share one memory region. That is, various layouts have been proposed for a two-port (also referred to as dual-port) SRAM that enables accesses to one memory cell from two ports.
For example, Japanese Patent Laid-Open No. 2002-43441 (Patent Document 1) and Japanese Patent Laid-Open No. 2002-237539 (Patent Document 2) disclose a structure in which of a P-well region and an N-well region in which each MOS transistor constituting a multi-port SRAM is disposed, the P-well region is divided into two regions and disposed on both sides of the N-well region.
For example, Japanese Patent Laid-Open No. 2004-47529 (Patent Document 3) discloses a structure in which well regions are arranged in order of P/N/P/N/P in a multi-port SRAM and in the P wells at both ends, a driver transistor is arranged, in each of the two N wells, a load transistor is arranged, and in the center P well, two access transistors are disposed.
For example, Japanese Patent Laid-Open No. 2006-339480 (Patent Document 4) discloses a structure in which a source contact of a driver transistor is short-circuited by an internal metal wire in an SRAM cell.
For example, Japanese Patent Laid-Open No. 2003-60089 (Patent Document 5) discloses a layout structure in which a P well is caused to be independent for each cell and the boundaries with cells neighboring to the right and left are constituted by an N well in an SRAM.
For example, Japanese Patent Laid-Open No. 2004-335535 (Patent Document 6) discloses a method of reducing coupling noises between word lines in a dual-port SRAM.
For example, Non-Patent Document 1 (“Proceedings of ICICDT”, 2008, pp. 55 to 58) discloses a structure of an SRAM having well separation regions in three positions.